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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 4 1 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. features ? 100 percent bus utilization no wait cycles between read and write internal self-timed write cycle individual byte write control single r/w (read/write) control pin clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining for tqfp power down mode common data inputs and data outputs cke pin to enable clock and suspend operation jedec 100-pin tqfp, 119 pbga package v dd +2.5v power supply ( 5%) v ddq : 2.5v i/o supply voltage industrial temperature available description the 18 meg 'nvp' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. they are organized as 524, 288 words by 36 bits and 1m words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defines the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 512k x 36 and 1m x 18 pipeline 'no wait' state bus sram preliminary information september 2002 fast access time symbol parameter -133 -166 units t kq clock access time 4.2 3.6 ns t kc cycle time 7.5 6 ns frequency 133 166 mhz
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? adv we } bw ? x (x=a,b,c,d or a,b) ce ce2 ce2 control logic 512kx36; 1mx18 memory array write address register write address register control logic output register buffer address register a [0:18] or a [0:19] clk cke a2-a18 or a2-a19 a0-a1 a'0-a'1 burst address counter mode data-in register data-in register control register oe zz 36 or 18 k k dqa0-dqd7 or dqa0-dqb8 dqpa-dqpd k k block diagram
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? pin configuration 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a18 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwd synchronous byte write enable we write enable v ss ground for core nu not usable nc not connected cke clock enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode b urst sequence mode selection v dd +2.5v power supply v ssq ground for output buffer v ddq isolated output buffer supply:2.5v zz snooze enable dqpa-dqpd parity data i/o 512k x 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqpb dqb8 dqb7 vddq vss q dqb6 dqb5 dqb4 dqb3 vss q vddq dqb2 dqb1 vss vdd vdd zz dqa8 dqa7 vddq vss q dqa6 dqa5 dqa4 dqa3 vss q vddq dqa2 dqa1 dqpa dqpc dqc1 dqc2 vddq vss q dqc3 dqc4 dqc5 dqc6 vss q vddq dqc7 dqc8 vdd vdd vdd vss dqd1 dqd2 vddq vss dqd3 dqd4 dqd5 dqd6 vss q vddq dqd7 dqd8 dqpd a6 a7 ce ce2 bwd bwc bwb bwa ce2 vdd vss clk we clk oe adv a18 a17 a8 a9 m ode a5 a4 a3 a2 a1 a0 nu nc vss vdd nc nc a10 a11 a12 a13 a14 a15 a16
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? pin configuration 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a19 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwb synchronous byte write enable we write enable cke clock enable vss ground for core nu not usable nc not connected ce , ce2, ce2 synchronous chip enable oe output enable dq1-dq16 synchronous data input/output mode bu rst sequence mode selection v dd +2.5v power supply v ssq ground for output buffer v ddq isolated output buffer supply: +2.5v zz snooze enable dqp1-dqp2 parity data i/o dqp1 is parity for dq1-8; dqp2 is parity for dq9-16 1m x 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a18 nc nc vddq vss q nc dqp1 dq8 dq7 vss q vddq dq6 dq5 vss vdd vdd zz dq4 dq3 vddq vss q dq2 dq1 nc nc vss q vddq nc nc nc nc nc nc vddq vss q nc nc dq9 dq10 vss q vddq dq11 dq12 vdd vdd vdd vss dq13 dq14 vddq vss q dq15 dq16 dqp2 nc vss q vddq nc nc nc a6 a7 ce ce2 nc nc bwb bwa ce2 vdd vss clk we clk oe adv a19 a17 a8 a9 m ode a5 a4 a3 a2 a1 a0 nu nc vss vdd nc nc a10 a11 a12 a13 a14 a15 a16
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? synchronous truth table (1) address operation used ce ce ce ce ce 1 ce2 ce ce ce ce ce 2 adv we we we we we bw bw bw bw bw x oe oe oe oe oe cke cke cke cke cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy r ead external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock curr ent address x xxxxxxh notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation finally depends on status of asynchronous pins (zz and oe ). burst read deselect burst write begin read begin write read write read write burst burst burst ds ds ds read ds ds read write write burst burst write read state diagram
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? asynchronous truth table (1) operation zz oe oe oe oe oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x18) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. write truth table (x36) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? interleaved burst address table (mode = v dd ) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?65 to +150 c p d power dissipation 1.6 w v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to gnd for ?0.3 to 3.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 3.3v 5% power supply characteristics (1) (over operating range) -133 -166 max max symbol parameter test conditions x18 36 x18 x32/36 uni t i cc ac operating device selected, 370 400 410 440 ma supply current oe = v ih , zz v il , all inputs 0.2v or v dd ? 0.2v, cycle time t kc min. i sb standby current device deselected, 160 160 210 210 ma ttl input v cc = max., all inputs 0.2v or v dd ? 0.2v, zz v il , f = max. i sbi standby current all inputs = v dd - 0.2 or 0.2v 10 10 10 10 ma cmos input clook = v ss note: 1. nu pin must be low or not connected dc electrical characteristics (over operating range) 2.5v symbol parameter test conditions min. max. unit v oh output high voltage i oh = ?1.0 ma (2.5v) 2.0 ? v i oh = ?100 a (2.5v) v dd -0.2 ? v ol output low voltage i ol = 1.0 ma (2.5v) ? 0.4 v i ol = 100 a (2.5v) ? 0.2 v ih input high voltage 1.7 v dd + 0.3 v v ihi input high voltage for mode pin v dd -0.3 v dd + 0.3 v v ili input high voltage for mode pin and nu pins -0.3 0.3 v v il input low voltage ?0.3 0.7 v i li input leakage current v in = 0 to v dd (1) ?1 1 a i nu input current (nu pin) v in = 0v to 0.3v -1 1 a i lo output leakage current gnd v out v ddq , oe = v i ?1 1 a
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = gnd 7 pf c in input capacitance for v in = gnd 10 pf mode, zz, nu pin c i / o input/output capacitance v i / o = gnd 9 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1v/ ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 ? 1.25v 50 ? output c l =20p f 295 ? 5 pf including jig and scope 217 ? output +2.5v figure 3 figure 4 2.5v i/o output load equivalent
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? read/write cycle switching characteristics (1) (over operating range) -133 -166 symbol parameter min. max. min. max. unit fmax clock frequency ? 133 ? 166 mhz t kc cycle time 7.5 ? 6 ? ns t kh clock high time 3 ? 2.2 ? ns t kl clock low time 3 ? 2.2 ? ns t kq clock access time ? 4.2 ? 3.6 ns t kqx (2) clock high to output invalid 1.5 ? 1.5 ? ns t kqlz (2,3) clock high to output low-z 0 ? 0 ? ns t kqhz (2,3) clock high to output high-z ? 3.5 ? 3.5 ns t oeq output enable to output valid ? 4.2 ? 3.8 ns t oelz (2,3) output enable to output low-z 1.5 ? 1.5 ? ns t oehz (2,3) output disable to output high-z 1.5 4.2 1.5 3.8 ns t as address setup time 2 ? 1.5 ? ns t ws read/write setup time 2 ? 1.5 ? ns t ces chip enable setup time 2 ? 1.5 ? ns t se clock enable setup time 2 ? 1.5 ? ns t avs address advance setup time 2 ? 1.5 ? ns t ds data setup time 1.7 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t he clock enablehold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t advh address advance hold time 0.5 ? 0.5 ? ns t dh data hold time 0.5 ? 0.5 ? ns t pds zz high to power down ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? sleep mode timing sleep mode electrical characteristics symbol parameter cond itions min. max. unit i sb 2 current during sleep mode zz v ih 20 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns don't care deselect or read only deselect or read only t rzzi k zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? read cycle timing t ds clock adv a17 - a0 or a18 - a0 we cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined notes: we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? write cycle timing t ds t dh clock adv a17 - a0 or a18 - a0 we cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined notes: we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz q0-3 q0-4
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? single read/write cycle timing clock cke address write ce adv oe data out data in d5 t se t he t kh t kl t kc don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? cke cke cke cke cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clock cke address write ce adv oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? ce ce ce ce ce operation timing don't care undefined clock cke address write ce adv oe data out data in t se t he t kh t kl t kc notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d5 d2 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. 00a 09/06/02 is61nvp51236 is61nvp10018 issi ? ordering information commercial range: 0c to +70c frequency order part number package 512kx36 166 is61nvp51236-166tq tqfp 133 is61nvp51236-133tq tqfp 1mx18 166 is61nvp10018-166tq tqfp 133 is61nvp10018-133tq tqfp industrial range: ? 40c to +85c frequency order part number package 512kx36 166 is61nvp51236- 166tqi tqfp 133 is61nvp51236- 133tqi tqfp 1mx18 166 is61nvp10018- 166tqi tqfp 133 is61nvp10018- 133tqi tqfp

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